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Chapter 4: FSM Concepts in Verilog

Introduction

Finite State Machines (FSMs) are models used to design logic that transitions between a set of defined states based on input signals and clock edges. They’re critical for implementing control logic in processors, communication protocols, peripheral controllers, and more.

FSMs are composed of:

  • States: Defined conditions or modes of operation
  • Transitions: Movement between states based on input
  • Outputs: Signals determined by the current state or combination of state and inputs

4.1 Moore vs. Mealy FSMs

There are two main types of FSMs based on how the outputs are determined:

  • Moore FSM: Outputs are based only on the current state. This often results in more stable output signals.
  • Mealy FSM: Outputs are based on both the current state and the current inputs. This can reduce the number of states but adds complexity.

Example Comparison:

CharacteristicMooreMealy
Output Depends OnStateState + Input
TimingChanges on clock edgeMay change immediately on input
Design ComplexitySimplerPotentially fewer states

4.2 State Diagrams and State Encoding

State diagrams are a visual way to describe FSM behavior. States are shown as labeled circles, and transitions are arrows labeled with the input condition (and output, in Mealy FSMs).

Text-based Example (Moore):

    [IDLE] -- go=1 --> [LOAD]
    [LOAD] -- done=1 --> [DONE]
    [DONE] -- reset=1 --> [IDLE]

State Encoding Techniques

To implement FSMs in Verilog, states must be represented by binary codes. Here are some common encoding strategies:

  • Binary: Uses the fewest flip-flops, but can result in complex logic.
  • One-hot: Uses one flip-flop per state (only one bit is 1 at a time). Easier for synthesis tools and FPGAs.
  • Gray Code: Ensures only one bit changes between adjacent states. Good for asynchronous transitions.

Example: One-hot encoding


    parameter IDLE = 3'b001, LOAD = 3'b010, DONE = 3'b100;
    reg [2:0] state, next_state;

4.3 FSM Implementation Tips

  • Use parameter to name states for readability
  • Separate blocks for state transition logic and output logic help modularity
  • Use always @(posedge clk) for state transitions
  • Reset logic is critical—always initialize the FSM to a known state
  • Simulate with corner-case inputs and verify all transitions

Summary

  • FSMs provide a clear way to control digital systems using defined state behavior
  • Moore machines simplify timing; Mealy machines offer compactness
  • State encoding affects area, speed, and logic complexity
  • Visual diagrams and truth tables help clarify system behavior

🧪 MicroSim

Link to Simulation Demo

✅ Quiz: Check Your Understanding

1. What makes a Moore FSM's output more stable than a Mealy FSM?

  • A) Inputs are ignored
  • B) Outputs change only on state transitions
  • C) States use fewer bits
  • D) No clock is required
Show Answer

Correct answer: B) Outputs change only on state transitions

2. Which encoding uses one flip-flop per state?

  • A) Binary
  • B) Gray
  • C) One-hot
  • D) ASCII
Show Answer

Correct answer: C) One-hot

3. What does a state diagram represent?

  • A) Memory hierarchy
  • B) Logic timing
  • C) State transitions and outputs
  • D) Flip-flop layout
Show Answer

Correct answer: C) State transitions and outputs