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Chapter 4: Verilog Modeling Techniques

Introduction

Verilog supports two primary modeling styles: behavioral and structural. These styles allow designers to either describe what the circuit should do (behavioral) or how it is constructed from smaller components (structural). Understanding both is key to writing effective and efficient Verilog code.

4.1 Behavioral and Structural Modeling

Behavioral modeling focuses on the intended functionality of a module, using high-level constructs such as if, case, and procedural blocks. It is commonly used in early design phases and testbenches.

Structural modeling explicitly connects lower-level modules (like gates or other modules) to form a design. It reflects the physical design more closely. 

// Behavioral example
    module mux2(input sel, input a, input b, output reg y);
      always @(*)
        if (sel) y = b;
        else     y = a;
    endmodule
    
    // Structural example
    module and2(input a, input b, output y);
      assign y = a & b;
    endmodule

4.2 Continuous Assignments

Continuous assignments are used to model combinational logic and are defined with the assign keyword. They operate continuously as input values change. 

assign y = a & b;

Only wire types can be driven by assign statements.

4.3 Procedural Blocks

Procedural blocks describe behavior in sequential logic. There are two kinds:

  • initial: Executes once at the beginning of simulation (used in testbenches).
  • always: Executes repeatedly when its sensitivity list is triggered.
// Example: toggling a signal
    reg clk;
    initial begin
      clk = 0;
      forever #5 clk = ~clk;
    end
    
    // Example: register update
    always @(posedge clk) begin
      q <= d;
    end

4.4 Blocking vs. Non-blocking Assignments

Verilog has two types of assignments inside procedural blocks:

  • =: Blocking assignment (executes sequentially)
  • <=: Non-blocking assignment (executes in parallel with other non-blocking assignments)

Use = in initial and always @(*) for combinational logic, and <= in always @(posedge clk) for sequential logic. 

// Correct
    always @(posedge clk) begin
      q1 <= d1;
      q2 <= d2;
    end

Summary

  • Behavioral modeling describes what a circuit does.
  • Structural modeling describes how a circuit is built.
  • assign is used for continuous combinational assignments.
  • always and initial blocks define procedural behavior.
  • Use <= for clocked (sequential) logic to avoid race conditions.

🧪 MicroSim

Link to Simulation Demo

✅ Quiz: Check Your Understanding

1. Which modeling style connects lower-level components?

  • A) Behavioral
  • B) Structural
  • C) Functional
  • D) Abstract
Show Answer

Correct answer: B) Structural

2. What does assign create in hardware?

  • A) Flip-flops
  • B) Testbench signals
  • C) Combinational logic
  • D) Memory arrays
Show Answer

Correct answer: C) Combinational logic

3. Which assignment operator should be used inside clocked always blocks?

  • A) =
  • B) :=
  • C) ==
  • D) <=
Show Answer

Correct answer: D) <=