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Chapter 4: Verilog Basics

Introduction

Verilog is a hardware description language (HDL) used to model electronic systems. It allows designers to describe the structure and behavior of digital circuits and simulate their functionality before physical implementation.

This section covers the core syntax and structure of Verilog, including module definitions, ports, data types, and the basic building blocks used to create digital logic systems.

4.1 Verilog Syntax and Semantics

Verilog code is written using modules, which encapsulate design blocks. A module defines inputs, outputs, and internal behavior. 

module and_gate(input A, input B, output Y);
      assign Y = A & B;
    endmodule

Semicolons ; end statements, and blocks such as module...endmodule define structure.

4.2 Data Types in Verilog

Verilog supports various data types to represent logic values:

  • wire: Represents combinational logic connections.
  • reg: Holds a value in procedural blocks.
  • integer, real: Used for simulations and testbenches.

Example: 

reg [7:0] byte_reg;
    wire valid_signal;

4.3 Module Definition and Instantiation

A Verilog module defines a reusable component. It can be instantiated within other modules. 

// Define
    module inverter(input A, output Y);
      assign Y = ~A;
    endmodule
    
    // Instantiate
    inverter u1 (.A(signal_in), .Y(signal_out));

4.4 Inputs and Outputs

Ports allow communication between modules. Inputs, outputs, and bidirectional ports (inout) are declared in the module header. 

module my_module(
      input clk,
      input rst,
      output reg done
    );

Summary

  • Verilog modules define reusable design blocks.
  • wire and reg are used for different types of logic signals.
  • Module instantiation allows hierarchical design.
  • Syntax rules define structure and behavior of the code.

🧪 MicroSim

Link to Simulation Demo

✅ Quiz: Check Your Understanding

1. Which keyword declares a combinational connection?

  • A) reg
  • B) wire
  • C) assign
  • D) input
Show Answer

Correct answer: B) wire

2. What is the correct way to declare an 8-bit register?

  • A) reg [8] data;
  • B) reg [0:7] data;
  • C) reg [7:0] data;
  • D) wire [7:0] data;
Show Answer

Correct answer: C) reg [7:0] data;

3. Which block is used to define test stimulus in simulation?

  • A) assign
  • B) module
  • C) initial
  • D) always
Show Answer

Correct answer: C) initial