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Chapter 6: Simulation & Debugging in Digital Design

Introduction

Before a digital design can be implemented in hardware, it must be rigorously tested to ensure functional correctness and timing accuracy. Simulation and debugging are essential stages in the design flow that allow engineers to validate behavior, identify logic flaws, and fine-tune performance—all before committing to silicon or programming an FPGA. This section explores the tools, methodologies, and best practices used to simulate and debug digital designs effectively.

6.1 Simulation & Debugging: Techniques for Verifying Digital Designs

Simulation and debugging are critical stages in the digital design process. They ensure that your hardware behaves as intended before deployment on actual silicon or an FPGA.

Types of Simulation

  • Functional Simulation: Validates the logic and functional correctness of the design without regard to timing. Ideal for early-stage verification.
  • Timing Simulation: Incorporates delays after synthesis and implementation to detect issues like race conditions and setup/hold violations.

Common Simulation Tools

  • Open-source: Icarus Verilog, GHDL
  • Commercial: ModelSim, Vivado Simulator, QuestaSim

Debugging Techniques

  • Waveform Analysis: Observe signal transitions over time using tools like GTKWave or ModelSim’s built-in viewer.
  • Assertions: Add conditions in your testbench to check if specific behaviors occur during simulation.
  • Testbenches: Create environments to drive inputs and check outputs for your module under test (MUT).
  • Signal Tapping (in FPGA): Use logic analyzers like Vivado ILA to inspect internal signals on hardware.

Example Flow

  1. Write your Verilog/VHDL module.
  2. Create a testbench that applies stimuli and checks responses.
  3. Simulate using a tool like Icarus Verilog or ModelSim.
  4. Debug issues by inspecting waveforms and refining your design.

✅ Quiz: Check Your Understanding

1. What is the primary purpose of functional simulation?

  • A) To determine power usage
  • B) To validate logic behavior
  • C) To optimize placement of logic elements
  • D) To generate bitstreams
Show Answer

Correct answer: B) To validate logic behavior

2. What tool can you use to visually inspect waveforms from a simulation?

  • A) Git
  • B) Vivado ILA
  • C) GTKWave
  • D) Quartus Programmer
Show Answer

Correct answer: C) GTKWave

3. Why are assertions useful in a testbench?

  • A) They increase simulation speed
  • B) They automate HDL synthesis
  • C) They check for expected behavior during simulation
  • D) They help compress bitstreams
Show Answer

Correct answer: C) They check for expected behavior during simulation

🛠️ Project: Simulate and Debug a 2-bit Counter

Objective

Apply simulation and debugging techniques to validate a simple digital circuit.

Task

Design, simulate, and debug a 2-bit counter using Verilog and a simulation tool of your choice.

Expected Learning

You will gain hands-on practice creating functional testbenches, running simulations, and analyzing waveforms to find and fix problems early in the design flow.

Instructions

  1. Write a Verilog module for a 2-bit counter that:
    • Has inputs clk (clock) and rst (reset).
    • Increments the count on each rising edge of clk.
    • Resets to 0 when rst is asserted.
  2. Write a Verilog testbench that:
    • Drives the clock signal with a regular period.
    • Pulses the reset at the beginning of the simulation.
    • Lets the counter run for at least 8 clock cycles.
  3. Simulate your design using a tool such as:
    • EDA Playground (browser-based, free)
    • Icarus Verilog + GTKWave (open-source)
    • ModelSim, Vivado Simulator, or other commercial tools
  4. Capture and analyze a waveform showing:
    • The clock signal (clk)
    • The reset signal (rst)
    • The 2-bit counter output (count[1:0])
  5. Debug and refine your design:
    • Ensure the counter resets correctly after rst goes high.
    • Confirm that the counter counts 0 → 1 → 2 → 3 → 0 cyclically.
    • Identify and correct any timing or functional issues.

Deliverables

  • Verilog source file for your 2-bit counter (counter_2bit.v)
  • Verilog testbench file (tb_counter_2bit.v)
  • Screenshot of the waveform display showing correct operation
  • Short writeup (~½ page) summarizing:
    • Any issues encountered
    • How you identified and fixed them

Tips

  • Use $dumpfile and $dumpvars in your testbench to generate waveforms if using Icarus Verilog.
  • Make sure your clock is toggling at a consistent interval.
  • Observe the behavior carefully at reset and around the counter rollover from 3 to 0.